Performance of complimentary metal oxide semiconductor (CMOS) devices have been enhanced via increases in drive current achieved via strain induced band structure modification. Channel regions formed in a silicon layer under biaxial tensile strain have allowed enhanced electron mobility to be realized for N-channel or NMOS devices. This is accomplished via formation of the silicon layer on an underlying relaxed semiconductor alloy layer, such as a silicon-germanium layer, which in turn is formed on the underlying semiconductor substrate. In addition, enhanced hole mobility can be realized via formation of a P-channel or PMOS device in a silicon-germanium layer with biaxial compressive strain. The presence of the performance enhancing silicon-germanium layer however presents difficulties during subsequent metal silicide formation processes. For example, silicidation processes, applied to a CMOS source/drain region will consume part or all of the silicon-germanium layer overlying the source/drain region. During the silicidation process, germanium atoms tend to segregate and accumulate at the surfaces of the metal silicide grains. The resulting germanium-rich interfacial layer at the surface of the metal silicide grains behave as a diffusion barrier and retard complete formation of the desired metal silicide layer, thus resulting in a lower than desired conductivity of the metal silicide layer when compared to metal silicide counterparts formed from non-semiconductor alloy layers. The decrease in metal silicide conductivity or the increase in metal silicide resistance will negatively influence CMOS performance.